Difference between revisions of "RISC"
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The idea was inspired by the discovery that many of the features that were included in traditional CPU designs to facilitate coding were being ignored by the programs that were running on them. Also these more complex features took several processor cycles to be performed. In addition, the speed of the CPU in relation to the memory it accessed was increasing. This led to a number of techniques to streamline processing within the CPU, while at the same time attempting to reduce the total number of memory accesses. | The idea was inspired by the discovery that many of the features that were included in traditional CPU designs to facilitate coding were being ignored by the programs that were running on them. Also these more complex features took several processor cycles to be performed. In addition, the speed of the CPU in relation to the memory it accessed was increasing. This led to a number of techniques to streamline processing within the CPU, while at the same time attempting to reduce the total number of memory accesses. | ||
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Revision as of 07:02, 22 February 2015
Reduced Instruction Set Computing (RISC), is a microprocessor CPU design philosophy that favors a smaller and simpler set of instructions that all take about the same amount of time to execute. Well known RISC families include DEC Alpha, ARC, ARM, AVR, MIPS, PA-RISC, PIC, Power Architecture (including PowerPC), SuperH (used in the Sega 32X, Sega Saturn and Sega Dreamcast), and SPARC.
The idea was inspired by the discovery that many of the features that were included in traditional CPU designs to facilitate coding were being ignored by the programs that were running on them. Also these more complex features took several processor cycles to be performed. In addition, the speed of the CPU in relation to the memory it accessed was increasing. This led to a number of techniques to streamline processing within the CPU, while at the same time attempting to reduce the total number of memory accesses.