Difference between revisions of "SH-2"

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"The SH2 is a small (2 cm square) but fast RISC chip that has been designed primarily to process graphics. Like all RISC processors, it's more streamlined that conventional CISC-based chips and carries out instructions in far fewer clock cycles." — ''Next Generation''
 
"The SH2 is a small (2 cm square) but fast RISC chip that has been designed primarily to process graphics. Like all RISC processors, it's more streamlined that conventional CISC-based chips and carries out instructions in far fewer clock cycles." — ''Next Generation''
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==Technical specifications==
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* Clock rate: 28.63636 MHz{{intref|Sega Saturn hardware notes (2004-04-27)}}{{fileref|Hitachi SuperH Programming Manual.pdf}}{{fileref|SH7604 Hardware Manual.pdf}}
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** CPU core: 32‑bit [[wikipedia:Reduced instruction set computing|RISC]] instructions/[[wikipedia:Processor register|registers]], 37.227268 [[wikipedia:Instructions per second|MIPS]] (1.3 MIPS per MHz),{{fileref|SH-2A.pdf|page=2}}{{ref|[https://www.renesas.com/en-eu/products/microcontrollers-microprocessors/superh/sh7040/sh7040.html SH7040, SH7041, SH7042, SH7043, SH7044, SH7045], Renesas}} up to 2 instructions per cycle{{fileref|Hitachi SuperH Programming Manual.pdf|page=390}}
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** DMA unit: DMAC (Direct Memory Access Controller),{{fileref|SH7604 Hardware Manual.pdf|page=3}} parallel processing{{fileref|SH7604 Hardware Manual.pdf|page=219}}
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** 2 internal [[wikipedia:Fixed-point arithmetic|fixed‑point]] math processors:{{fileref|Sega Service Manual - Sega Saturn (PAL) - 013-1 - June 1995.pdf}} MULT multiplier DSP,{{fileref|SH7604 Hardware Manual.pdf|page=3}}{{fileref|SH7604 Hardware Manual.pdf|page=22}}{{fileref|ST-103-R1-040194.pdf|page=23}} DIVU division unit,{{fileref|SH7604 Hardware Manual.pdf|page=3}}{{fileref|SH7604 Hardware Manual.pdf|page=22}} parallel processing{{fileref|SH7604 Hardware Manual.pdf|page=303}}
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*** MULT multiplier DSP: 28.63636 MOPS fixed-point math (1 operation per cycle){{fileref|Hitachi SuperH Programming Manual.pdf|page=31}}
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*** DIVU division unit: 16/32/64-bit division,{{fileref|SH7604 Hardware Manual.pdf|page=303}} 734,265 divides/sec (39 cycles per divide){{fileref|Hitachi SuperH Programming Manual.pdf|page=155}}
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** [[wikipedia:Bus (computing)|Bus]] width: 64‑bit (2× 32‑bit) internal, 32‑bit external{{fileref|ST-103-R1-040194.pdf}}
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** Word length: [[32-bit era|32-bit]]
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** Supports [[wikipedia:Master/slave (technology)|Master/Slave]] configuration with dual SH-2
  
 
==Documentation==
 
==Documentation==

Revision as of 08:27, 6 November 2016

The SH-2 is a 32-bit RISC processor developed by Hitachi (and currently produced by Renesas) as part of the SuperH family.


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The Sega Saturn is powered by two Hitachi SH2, 32-bit RISC processors. These particular SH-2 chips run at 28.6364 MHz (versions were developed which ran as high as 40 MHz), and are capable of processing up to 37.22732 million instructions per second (MIPS) each (1.3 MIPS per MHz),[1][2] for a combined rating of 74.45464 MIPS (MIPS however, is not a true indication of processor performance in many cases). Each SH2 comes with an internal 4 KB RAM cache in order to speed up processing tasks.

"The SH2 is a small (2 cm square) but fast RISC chip that has been designed primarily to process graphics. Like all RISC processors, it's more streamlined that conventional CISC-based chips and carries out instructions in far fewer clock cycles." — Next Generation

Technical specifications

  • Clock rate: 28.63636 MHz[3][4][5]
    • CPU core: 32‑bit RISC instructions/registers, 37.227268 MIPS (1.3 MIPS per MHz),[1][2] up to 2 instructions per cycle[6]
    • DMA unit: DMAC (Direct Memory Access Controller),[7] parallel processing[8]
    • 2 internal fixed‑point math processors:[9] MULT multiplier DSP,[7][10][11] DIVU division unit,[7][10] parallel processing[12]
      • MULT multiplier DSP: 28.63636 MOPS fixed-point math (1 operation per cycle)[13]
      • DIVU division unit: 16/32/64-bit division,[12] 734,265 divides/sec (39 cycles per divide)[14]
    • Bus width: 64‑bit (2× 32‑bit) internal, 32‑bit external[15]
    • Word length: 32-bit
    • Supports Master/Slave configuration with dual SH-2

Documentation

References